This invention relates in general to integrated circuit testing, and more particularly to parallel testing of semiconductor memory circuits.
Semiconductor memories, also known as dynamic random access memories (DRAM) or static random access memories (SRAM), have become increasingly important components in many electronic circuits. To insure high quality, the semiconductor memories must be extensively tested before a manufacturer ships product to a customer. Recently, semiconductor memories have increased dramatically in complexity so that one to four million memory cells can be formed in a single integrated circuit. Testing such complex circuits requires a significant amount of time in the range of five to ten minutes per circuit or more.
To minimize test time, testers have been developed which can test a plurality of chips in parallel. These testers allow up to 32 memory circuits to be tested in essentially the same time as a single memory circuit. Parallel memory testers have been used to test packaged semiconductor memories for some time.
A large portion of the cost of manufacturing an integrated circuit is incurred in packaging the integrated circuit. It is desirable to package only functional integrated circuits so that packaging cost is not incurred on devices which will be thrown away. Testing semiconductor memories in chip or wafer form, before packaging, requires as much time as testing after packaging. Due to the close spacing of contact pads which are formed on the semiconductor memories, however, it has been difficult to make contact to enough integrated circuits to make parallel testing practical. When testing integrated circuits in chip or wafer form, the contact pads are usually coupled to a tester by probe needles which are mounted on a probe card or similar device. The probe needles must be aligned to the pattern of contact pads on the integrated circuit and must remain aligned through many test cycles. This alignment problem becomes more difficult as more probe needles are added to the probe card. This problem has made it virtually impossible to test more than four integrated circuits in parallel in chip or wafer form.
In addition to the alignment problem with probe needles, any non-planarity in the semiconductor wafer created difficulty in contacting all of the contact pads. As attempts were made to place more needles in contact with the wafer, this co-planarity problem becomes more acute. Although probe cards have been made with probe needles which can test up to four semiconductor memories in parallel, due to the difficulties set out above operating speed is low, maintenance cost is high and reliability is compromised.
Access time is a figure of merit for semiconductor memories. Memories must be tested at high speed and sorted into groups having similar access times. Conventional probe needle testing does not allow this high speed testing, and so the sorting operation could only be done after the devices were packaged. This made it difficult to predict availability of a memory of a particular access time group until the very end of the assembly process. It is advantageous to know the access time of a memory as early as possible, preferably when the memories are still in wafer form.
Recently, membrane probe card technology has been used to probe integrated circuit chips with closely spaced contact pads. This technology was described by B. Leslie and F. Matta in "Membrane Probe Card Technology (The Future for High Performance Wafer Test)," presented at the 1988 IEEE International Test Conference. This technology has been used to replace probe needles with probe bumps which are formed on a flexible membrane. However, since chips were still tested individually, little improvement was realized in process cycle time.
Accordingly, it is an object of the present invention to provide a method for testing integrated circuits in parallel prior to packaging.
It is another object of the present invention to provide a method of testing semiconductor memories without probe needles.
It is a further object of the present invention to provide a method of testing integrated circuits which compensates for co-planarity problems.
It is a further object of the present invention to provide a method of testing semiconductor memories with higher throughput and lower cost.
Another object of the present invention is to provide a method of testing semiconductor memories which allows high speed testing to be completed in wafer form.
It is another object of the present invention to provide a method of testing semiconductor memories which takes advantage of testers which are capable of testing a plurality of memories in parallel.